1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a data cache memory.
2. Description of the Prior Art
A computer system is composed of major building blocks including, but not limited to, the processor, main memory, and control logic. The processor often requires data to perform calculations, which it obtains from main memory, typically a very large Dynamic Random Access Memory (DRAM). As computer microprocessors have become faster and faster, the rate at which data must be supplied to them must increase as well. Unfortunately, the rate at which DRAMs can operate is usually much slower than the speed of the microprocessor in the same computer system. Therefore, when the microprocessor requests data from main memory it may have to wait several cycles, during which time it is idle and unproductive. These unproductive cycles are referred to as "wait states" since the microprocessor simply waits for the needed data to be provided by main memory.
Cache memories provide a valuable tool for increasing computer system performance by reducing or even eliminating microprocessor wait states. The cache memory has a very fast data cache in which a copy of a portion of main memory data is stored. This data cache is much faster than the main memory, and so it can supply data to the microprocessor very quickly, possibly before it incurs a wait state.
The typical cache subsystem is comprised of five blocks: microprocessor, main memory, tag RAM, data cache, and control logic. When the microprocessor requests information, a read signal is immediately sent to both the main memory and the tag RAM. The tag RAM holds the address locations of all data which is stored in the data cache. The tag RAM compares the requested memory address with the memory addresses of all data stored in the data cache. If the requested memory address is in the tag RAM, a "hit" condition exits, and data from that location will be gated from the data cache to the microprocessor. In a "hit" condition, the tag RAM generates a compare Match output signal. In the hit condition, the data cache gates the required data onto the data bus before the main memory can respond. In this way, microprocessor wait states are avoided. However, if the tag RAM's comparison operation indicates that the desired data is not stored inside the data cache, a "miss" condition exists, and the data must come from main memory. As a result, microprocessor wait states are incurred and overall computer performance is compromised.
The mechanism for reading data from the data cache is efficient and straightforward. During cache reads, the data cache can typically be read before the tag RAM indicates whether a hit or miss condition exists. Therefore, the data cache can be read in parallel to the tag comparison; if the tag RAM registers a "hit" condition, the data cache outputs are enabled immediately. If a "miss" condition exists, the outputs are not enabled and main memory will ultimately drive the data bus. This parallel activity saves time and can result in the data being read in a single cycle with no microprocessor wait states.
Sometimes it becomes necessary to update the information stored inside the data cache by performing a data cache write. For data cache writes, the parallel activity associated with data cache reads is not possible with most SRAMS used for data caches. In a data cache write, the write can only occur once a "hit" is registered from the tag RAM; otherwise, erroneous data might mistakenly be written in the data cache on a tag RAM "miss", and data coherency problems with the main memory could result. In other words, when the microprocessor is allowed to write to the data cache before a tag RAM "miss" condition is determined, the microprocessor will write data into a memory address location which does not correspond to a specific main memory address location. This could mean that, for a particular address location, the data stored in the data cache does not match the data stored in main memory. Because the compare operation of the tag RAM and the cache write occur serially, the write takes additional time, possibly causing microprocessor wait states.